Mechanical stresses within a semiconductor device substrate have been widely used to modulate device performance. For example, in common Si technology, the channel of a transistor is oriented along the {110} planes of silicon. In this arrangement, hole mobility is enhanced when the channel is under compressive stress in the film direction and/or under tensile stress in a direction normal of the channel, while the electron mobility is enhanced when the silicon film is under tensile stress in the film direction and/or under compressive stress in the direction normal of the channel. Therefore, compressive and/or tensile stresses can be advantageously created in the channel regions of a p-channel field effect transistor (p-FET) and/or an n-channel field effect transistor (n-FET) in order to enhance the performance of such devices.
One possible approach for creating a desirable stressed silicon channel region is to form embedded SiGe or Si:C stressors at the source and drain regions of a MOSFET to induce compressive or tensile strain therein in the channel region located between the source and drain regions. FIG. 1 shows a conventional MOSFET 102 with embedded SiGe stressors 114 and 116 at its source and drain regions 102S and 102D. Specifically, the source and drain regions 102S and 102D are located in a semiconductor substrate 110, which has an upper surface 110A and contains one or more isolation regions 112 for isolating the MOSFET 102 from adjacent devices. A channel region 102C is also located in the semiconductor substrate 110 and between the source and drain regions 102S and 102D. A gate stack that comprises a gate dielectric layer 122, a gate conductor 124, a gate metal silicide layer 126, and optional sidewall spacers 127 and 128 are formed over the channel region 102C. SiGe stressor structures 114 and 116 are formed in the source and drain regions 102S and 102D for applying compressive stress to the channel region 102C. The SiGe stressor structures have flat upper surfaces 114A and 116A that are parallel to and coplanar with the upper surface 110A of the semiconductor substrate 110.
Another approach for creating a desirable stressed silicon channel region is to form a stress-inducing dielectric capping layer, such as a compressively or tensilely stressed silicon nitride layer, over a MOSFET to induce compressive or tensile stress in the channel region located between the source and drain regions.
Besides stress engineering, different Si surface orientations have also been employed for mobility enhancement. By using {110} Si surface orientation instead of the commonly used {100} Si surface orientation, hole mobility in P-FET shows dramatic improvement.
In addition to the mobility enhancement, contact resistance reduction is also critical for improving MOSFET performance, and it is becoming more and more important with the drastically shrunken geometry and reduced channel resistance. One way to reduce contact resistance is to increase contact area. However, increased contact area is contradictory to the scaling requirements of high-density devices. Therefore, there is a need for innovative methods that can solve this problem.